library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECIDERG is
	Port ( g : in STD_LOGIC_VECTOR (15 downto 0);
		gin : in STD_LOGIC;
		gack : out STD_LOGIC;
		m : in STD_LOGIC_VECTOR (15 downto 0);
		min : in STD_LOGIC;
		mack : out STD_LOGIC;
		c : out STD_LOGIC;
		cstr : out STD_LOGIC;
		cack : in STD_LOGIC;
		clkin: in STD_LOGIC);
end DECIDERG;

architecture Behavioral of DECIDERG is
	type estados is(comp, envio);
	begin
		dados: process(clkin, gin, min, cack)
			variable estado: estados := comp;
			variable recg: STD_LOGIC := '0';
			variable recm: STD_LOGIC := '0';
			variable gd: STD_LOGIC_VECTOR(15 downto 0);
			variable md: STD_LOGIC_VECTOR(15 downto 0);
			variable cd: STD_LOGIC;
		begin
			if clkin'event and clkin = '1' then
				c <= '0';
				cstr <= '0';
				gack <= '0';
				mack <= '0';
				case estado is
					when comp =>
						if gin = '1' then
							gd := g;
							recg := '1';
							gack <= '1';
						end if;
						if min = '1' then
							md := m;
							recm := '1';
							mack <= '1';
						end if;
						if recg = '1' and recm = '1' then
							if gd > md then
								cd := '1';
							else
								cd := '0';
							end if;
							recg := '0';
							recm := '0';
							estado := envio;
						end if;
					when envio =>
						if cack = '1' then
							estado := comp;
						else
							c <= cd;
							cstr <= '1';
						end if;
				end case;
			end if;
	end process dados;
end Behavioral;